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(R)
STE180N10
N - CHANNEL 100V - 5.5 m - 180A - ISOTOP POWER MOSFET
TYPE STE180N10
s s s s s
V DSS 100 V
R DS(on) < 7 m
ID 180 A
TYPICAL RDS(on) = 5.5 m 100% AVALANCHE TESTED LOW INTRINSIC CAPACITANCE GATE CHARGE MINIMIZED REDUCED VOLTAGE SPREAD
INDUSTRIAL APPLICATIONS: s SMPS & UPS s MOTOR CONTROL s WELDING EQUIPMENT s OUTPUT STAGE FOR PWM, ULTRASONIC CIRCUITS
ISOTOP
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symb ol V DS V DGR V GS ID ID I DM (*) P tot V ISO T s tg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) G ate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor Insulation Withstand Voltage (AC-RMS) Storage T emperature Max. Operating Junction Temperature
o o o
Value 100 100 20 180 119 540 450 3.6 2500 -55 to 150 150
( 1) ISD 180 , di/d 200 A/s, VDD V(BR)DSS, Tj TJMAX
Un it V V V A A A W W /o C V
o o
C C 1/8
(*) Pulse width limited by safe operating area
February 1999
STE180N10
THERMAL DATA
R thj -case R thc-h Thermal Resistance Junction-case Thermal Resistance Case-heatsink With conductive Grease Applied Max Max 0.27 0.05
o o
C/W C/W
AVALANCHE CHARACTERISTICS
Symbo l IAR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 25 V) Max Value 60 720 Unit A mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage I D = 1 mA Test Con ditions VGS = 0 Min. 100 50 500 400 Typ. Max. Unit V A A nA
V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = 20 V
T c = 125 oC
ON ()
Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 10 V Test Con ditions ID = 250 A I D = 90 A 180 Min. 2 Typ. 3 5.5 Max. 4 7 Unit V m A
V DS > ID(o n) x R DS(on )ma x V GS = 10 V
DYNAMIC
Symbo l g f s () C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz I D = 90 A V GS = 0 Min. 70 18 4 0.5 Typ. Max. Unit S nF nF nF
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STE180N10
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay T ime Rise Time Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 50 V I D = 90 A R G = 4.7 V GS = 10 V (Resistive Load, see fig. 3) V DD = 80 V ID = 180 A V GS = 10 V Min. Typ. 65 230 485 90 210 680 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbo l t d(on) tr tr (Voff) tf tc Parameter Turn-off Delay T ime Fall T ime Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions V DD = 50 V I D = 90 A V GS = 10 V R G = 4.7 (Resistive Load, see fig. 3) V DD = 80 V I D = 180 A V GS = 10 V R G = 4.7 (Induct ive Load, see fig. 5) Min. Typ. 280 100 100 170 260 Max. Unit ns ns ns ns ns
SOURCE DRAIN DIODE
Symbo l ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 180 A V GS = 0 250 1875 15 I SD = 180 A di/dt = 100 A/s T j = 150 o C V DD = 50 V (see test circuit, fig. 5) Test Con ditions Min. Typ. Max. 180 540 1.5 Unit A A V ns C A
() Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
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STE180N10
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STE180N10
Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
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STE180N10
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STE180N10
ISOTOP MECHANICAL DATA
DIM. MIN. A B C D E F G H J K L M N O 11.8 8.9 1.95 0.75 12.6 25.15 31.5 4 4.1 14.9 30.1 37.8 4 7.8 8.2 4.3 15.1 30.3 38.2 mm TYP. MAX. 12.2 9.1 2.05 0.85 12.8 25.5 31.7 MIN. 0.466 0.350 0.076 0.029 0.496 0.990 1.240 0.157 0.161 0.586 1.185 1.488 0.157 0.307 0.322 0.169 0.594 1.193 1.503 inch TYP. MAX. 0.480 0.358 0.080 0.033 0.503 1.003 1.248
G B
A
O
N D E F
J C K L M
H
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STE180N10
Information furnished is believed to be accurate and reliable. However, STMicroelect onics assumes no responsibil ity for the consequences r of use of such information nor for any infringement of patents or other rights of third partes which may result from its use. No license is i granted by implication or otherwise under any patent or patent rights of STMicroelectro nics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all informaton previously supplied. STMicroelectronics products i are not authorized for use as critical components in life support devices or systems with express written approval of STMicroelectronics. out The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysi - Malta - Mexico - Morocco - The Netherlands a Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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